DATA-PATH AND MEMORY ERROR COMPENSATION TECHNIQUE FOR LOW POWER JPEG IMPLEMENTATION
DSP Algorithm and Architecture Optimization for Hardware Implementation
Přednášející: Chaitali Chakrabarti, Autoři: Yunus Emre, Chaitali Chakrabarti, Arizona State University, United States
The paper presents a novel technique to mitigate effects of data-path and memory errors in JPEG implementations. These errors are mainly caused by voltage scaling and process variation in scaled technologies. We characterize the data-path and memory errors and derive a probability distribution of the total number of errors. We propose an algorithm-specific technique that corrects most errors after the quantization step in JPEG encoder by exploiting the characteristics of the quantized coefficients. Simulation results show that the proposed technique has a PSNR performance degradation of around 1.5 dB compared to the error-free case and 4 dB improvement compared to the no correction case at 0.75 bpp when BER=10^(-4). This is achieved with small circuitry overhead and no memory overhead.
Informace o přednášce
| Nahráno: | 2011-05-26 14:45 - 15:05, Club H |
|---|---|
| Přidáno: | 9. 6. 2011 23:29 |
| Počet zhlédnutí: | 24 |
| Rozlišení videa: | 1024x576 px, 512x288 px |
| Délka videa: | 0:16:30 |
| Audio stopa: | MP3 [5.63 MB], 0:16:30 |
Příbuzné přednášky
0:21:43
MULTI-RATE POLYPHASE DSP AND LMS CALIBRATION SCHEMES FOR OVERSAMPLED DATA CONVERSION SYSTEMS
DSP Algorithm and Architecture Optimization for Hardware Implementation
Přidáno: 9. 6. 2011 23:30
0:24:48
IMPROVING KERNEL-ENERGY TRADE-OFFS FOR MACHINE LEARNING IN IMPLANTABLE AND WEARABLE BIOMEDICAL APPLICATIONS
DSP Algorithm and Architecture Optimization for Hardware Implementation
Přidáno: 9. 6. 2011 23:09
Komentáře